Field of the Invention
The invention relates to a semiconductor device having a semiconductor chip and a system carrier being connected to it and having an island with an opening.
Semiconductor chips are mounted in a package, for the sake of protecting against destruction and against environmental factors, and for the sake of better manipulability. A plastic package is the preferred form for mass-produced products. Initially, the semiconductor chip is joined to a system carrier. The system carrier includes a frame, in which an island-like chip carrier and leads for the finished product are typically provided. Joining of the semiconductor chip to the system carrier, that is to the island that carries the chip, is typically carried out by adhesive bonding or alloying. After the semiconductor chip is mounted, its individual lead tips are connected to the leads of the carrier frame, for example with bonding wires. Subsequently, the semiconductor chip and the leads of the connecting frame are spray-coated in such a way that the semiconductor chip is completely encapsulated, and the leads of the package are electrically and mechanically accessible. Parts of the connection frame (lead frame) which are not needed are then removed by punching. The package is typically made of a hardening plastic molding compound.
Standardized plastic packages are becoming thinner and thinner. The TSOP model (Thin Small Outline Package), which is currently already in use, still has a package thickness of 1 mm. At the same time, the chips built into the packages are becoming larger. With chip dimensions greater than 10.times.10 MM.sup.2, package structures up to 20.times.20 mm.sup.2 are provided (TQFP=Thin Quad Flat Package). In thin plastic packages, the stabilizing effect of the plastic envelope is reduced. Since the connection of the chips to the island and the spray-coating with molding compound are carried out at temperatures of at least 180.degree. C., the coefficients of thermal expansion of the materials involved play a major role, especially in semiconductor devices with large lateral dimensions and extremely thin packages. Ideally, all of the coefficients of expansion should be the same, so that when the device cools down no bimetal effect can occur, and the chip and system carrier island sandwich cannot bend out of shape.
Actually, however, the coefficients of expansion of the primary materials vary greatly. Silicon has a coefficient of thermal expansion of 3, the molding composition of the package has a coefficient of thermal expansion of about 17, and a typical island material such as copper also has a coefficient of thermal expansion of about 17, each being given in units of ppm/K. An allowable extent of bending out of shape of the package is considered to be 30 .mu.m maximum, so that the coplanarity of the leads of the finished component will be assured during further processing, that is soldering.
One possibility for improving the bending performance is to use system carrier islands that are better adapted thermomechanically to silicon, with examples being NiFe alloys such as those known from German Published, Non-Prosecuted Patent Application DE 42 31 705 A1. However, ever-increasing scales of integration and ever-higher chip clock speeds, which cause higher power losses, argue against that. The heat dissipation and therefore heat conductivity of the NiFe alloys is 10 to 20 times worse than those of copper alloys. It is true that when the lead frame material is changed from copper to nickel-iron alloys, the heat resistance of a component does not increase in proportion to the differences between the heat conductivity coefficients. However, even if critical temperatures are not exceeded, higher chip temperatures lower the reliability and shorten the service life of the entire component. In order to provide for heat dissipation from circuits with high power loss, special packages with an inlaid heat distributor (heat slug) or with cooling bodies are then necessary, but are expensive and complicated to manufacture. System carrier islands with slits are known from U.S. Pat. Nos. 4,952,999 and 5,150,193. However, the latter patent also shows a system carrier with a central opening, having diameters which are smaller than the lateral chip dimensions, and having an area which is considerably smaller than the chip area. Both options lead to unacceptable sagging of the package.